#ChipScope Core Inserter Project File Version 3.0
#Sat Oct 11 10:20:16 CDT 2014
Project.device.designInputFile=D\:\\GitHub\\VHDL_Modules\\CODEC Wing\\DAC Test\\DACTest\\Square_wave_cs.ngc
Project.device.designOutputFile=D\:\\GitHub\\VHDL_Modules\\CODEC Wing\\DAC Test\\DACTest\\Square_wave_cs.ngc
Project.device.deviceFamily=13
Project.device.enableRPMs=true
Project.device.outputDirectory=D\:\\GitHub\\VHDL_Modules\\CODEC Wing\\DAC Test\\DACTest\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=BCLK_Chipscope
Project.filter<10>=Inst_PCM1754/output_buffer
Project.filter<11>=BCLK_OBUF
Project.filter<12>=BXLK_OBUF
Project.filter<13>=Inst_PCM1754/bclk_signal
Project.filter<14>=SCLK_OBUF
Project.filter<15>=Inst_PCM1754/SCLK_OBUF
Project.filter<16>=Inst_PCM1754/SCLK
Project.filter<17>=Inst_PCM1754
Project.filter<18>=port
Project.filter<1>=zeroa_signal
Project.filter<2>=zeroa
Project.filter<3>=SCLK_Chipscope
Project.filter<4>=LRCLK_Chipscope
Project.filter<5>=SDATA_Chipscope
Project.filter<6>=
Project.filter<7>=LED_OBUF
Project.filter<8>=CKfs
Project.filter<9>=Inst_PCM1754/lrclk_buffer
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=CK32_BUFGP
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=BCLK_Chipscope
Project.unit<0>.dataChannel<1>=SDATA_Chipscope
Project.unit<0>.dataChannel<2>=LRCLK_Chipscope
Project.unit<0>.dataChannel<3>=SCLK_Chipscope
Project.unit<0>.dataChannel<4>=zeroa_signal
Project.unit<0>.dataDepth=4096
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=5
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=BCLK_Chipscope
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=5
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
